1. Field of the Invention
The present invention relates to a semiconductor package, and in particular to a laminated semiconductor package in which semiconductor chip packages are laminated.
2. Description of the Related Art
In recent years, there have been proposed a variety of SiPs (System-in Packages) where a plurality of semiconductor chips is mounted on a single package in order to provide a predetermined system by the single package.
For example, FIG. 1 schematically shows a structure of a 3-chip-stack F-BGA (ball grid array) as one of the forms of SiP.
Referring to FIG. 1, a package 100 shown in FIG. 1 has a structure where an interposer 101 made of organic material, for example, with semiconductor chips 102, 103, 105 laminated thereon is sealed with a mold resin 107. Between the semiconductor chips 103 and 105 is inserted a spacer 104.
The semiconductor chip 102 mounted on the interposer 101 is for example a semiconductor chip including a logic device. The semiconductor chip 103 is configured with a semiconductor chip including a DRAM (dynamic random-access memory), and the semiconductor chip 105 is configured with a semiconductor chip including a flash memory. In other words, a semiconductor chip including the memory device is laminated on a semiconductor chip including the logic device. (For example, refer to JP-A-2001-36000 and JP-A-2005-72596.)
A semiconductor chip including a logic device generally has a problem of a large heating value. Especially in terms of the above package, the semiconductor chips in the upper layer (semiconductor chips 103, 105) are subjected to the influence of thermal radiation from the semiconductor chip in the lower layer (semiconductor chip 102). This degrades the reliability of system operation.
A solution to this problem is a laminated package where a package mounting a semiconductor chip including a logic device and a separate package mounting a semiconductor chip including a memory device are laminated one on the other.
FIG. 2 is an exemplary structure of a laminated package. Referring to FIG. 2, a laminated package (also called a package-on-package or PoP) 400 shown in FIG. 2 is for example a laminated package where an F-BGA package 200 is laminated on a package 300 as a flip-chip-type chip mounting substrate.
The package 300 has multilayer wirings on both face sides of a core substrate 301. On one face side of the multilayer wiring is mounted a semiconductor chip. On the other face side is formed a connecting section for connection to a mother board.
In the core substrate 301 is formed a via hole piercing the core substrate 301. A via-plug 308 is formed on the inner surface of the via hole. On the first face side (upper face side) of the core substrate 301 are laminated insulating layers 302, 303. In these insulating layers or on the insulating layers are laminated wiring structures 309, 310, 311 including pattern wirings and via-plugs to form a multilayer wiring structure.
On the wiring structure 311 as a top layer of the multilayer wiring is formed a solder resist layer 304 including an opening. On the wiring structure 311 exposed from the opening of the solder resist layer 304 is provided a bump 318 connected to a semiconductor chip 316. To the wiring structure 311 are connected solder balls 205 of the package 200.
On the second face side opposite to the first face side of the core substrate 301 is formed a same structure as the upper structure. That is, insulating layers 305, 306 are laminated and in these insulating layers or on the insulating layers are laminated wiring structures 312, 313, 314 including pattern wirings and via-plugs to form a multilayer wiring structure.
A solder resist layer 307 including an opening is formed to cover the wiring structure 314 as a bottom layer of the multilayer wiring. Further, to the wiring structure 314 exposed from the opening of the solder resist layer 307 are connected solder balls 315 for connection to a mother board, for example.
The package 200 is configured with, for example, F-BGA. On the interposer 201 are laminated semiconductor chips 202, 203 and the semiconductor chips 202, 203 are sealed with a mold resin 204. Under the interposer 201 are formed solder balls 205 electrically connected to the mounted semiconductor chips.
In the laminated package 400, for example the semiconductor chip 316 is a semiconductor chip including a logic device. The semiconductor chips 202, 203 are a semiconductor chips including memory devices.
This reduces the influence of heading of a semiconductor chip including a logic device on a semiconductor chip including a memory device, thus improving the system stability compared with a related art SiP.
One of the problems with the laminated package 400 is that it is difficult to support a larger number of pins in a semiconductor chip mounted on the package 200. In the laminated package 400, the semiconductor chip is mounted in a flip-chip structure on the package 300, as well as the package 200 being laminated on the package 300. This makes it difficult to form a connecting section for connecting the upper and lower packages, on a surface area where the semiconductor chip is mounted.
In recent years, even a memory semiconductor chip has accommodated more and more pins so that the structure of the package 400 could not support the semiconductor chip having multiple pins. It is also difficult for this type of laminated package to mount a semiconductor chip having multiple pins and including a logic device, on the upper layer.